SERDES
7620 - LatticeECP5/TRI-RATE SDI PHY IP Core: Can the device utilize 3G-SDI?
The Lattice ECP5 cannot support SDI Rx with a pathological pattern and, therefore, is not fully SDI-compliant. We do not recommend using the SDI solution on ECP5 unless the customer only requires SDI Tx.
4746 - LatticeECP3: How to check if the design uses the Clock Tolerance Circuit (CTC) inside the SerDes hard Physical Coding Sub-layer (PCS)?
The PCS has an option in GUI to enable or disable the CTC block while generating the PCS IP through IP Express in Lattice Diamond. If the CTC block has been enabled in GUI, the design will use it.
1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?
In the case of LatticeECP2M/LatticeECP3/LatticeSC/M SERDES/PCS QUADs, logic in the Link State Machine block generates the lsm_status*/ffs_ls_sync_status* signal. This logic is synchronous to the RX recovered clock. A single stage sync flop is OK to ...
1180 - While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?
It takes time even in an RTL simulation for the PLL models to lock to the reference clock. Please run the PCS simulation for about 100us. The PLL clocks will dynamically change until the PLL locks to the reference clock.
1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?
The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode. The assumption is that you are coding your own RTL 8b10b decoder in the fabric. Based on the definition of 8b10b codes , DATA=0x00 ...
525 - Where is LatticeECP2/M Serdes Reset RTL code ?
The Reset Sequence code for ECP2/M is included in Serdes demo package. http://www.latticesemi.com/dynamic/view_document.cfm?document_id=24513
1720 - LatticeECP3: If I am not using one of the SERDES/PCS quads of my device, are there any special considerations as far as layout is concerned?
If I don't want to use a quad of SERDES/PCS, what should I do with SERDES/PCS power and signal pins?
If you are not using SERDES/PCS, you need to do the following steps: 1. Connect power: VCCA and ground VSSA; 2. Let other power domains (VCCIB and VCCOB) floating; 3. Let the other signal pins such as ;HDINP/N, HDOUTP/N and REF-CLKP/N floating. all ...
2888 - How to handle unused power supply inputs for SERDES channels for the LatticeECP2/M device?
The SERDES design provides separate final stage Rx and Tx power nodes for each CML input and output buffer. These are identified as VCCIB and VCCOB for LatticeECP2/M. These allow the receiver input termination (50 Ohm, 75 Ohm, 2K Ohm) and transmitter ...
1619 - How do I measure the common mode voltage of LatticeECP3 SERDES current-mode logic (CML) signaling ?
LatticeECP3 SERDES uses current-mode logic (CML) signaling for high-speed pins such as PCS_HDOUTP/N, PCS_HDINP/N, and PCS_REFCLKP/N. In order to successfully communicate between two devices with CML signaling, the common mode voltage of CML signaling ...
998 - I need to connect an optical module to LatticeECP2/M SERDES. Can you provide an example interface circuit?
Refer to figure 9(CML/LVDS) and figure 10(CML/LVPECL) interface circuits in Lattice Technote, Electrical Recommendations for Lattice SERDES, TN1114. You may want to look at the specific module specifications you are considering.
1607 - What is the depth of Serdes down/up-sampling FIFOs?
The depth of Serdes down/up-sampling FIFOs is four. It is very shallow. It requires that the read and write clock to them come from the same clock source. Only phase difference between read and write clocks is allowed in order to make these FIFOs ...
990 - Are there any pins that can't be used when the SERDES is being used?
There are placement rules regarding keep-out areas near VCCRX and VCCTX, as well as pins adjacent to operational SERDES Quads. These are known as "aggressor I/O pins". If you are not using certain SERDES Quads, it is perfectly acceptable to use the ...
1601 - In Lattice ECP2M SerDes, I use continuous K character, BC as the training pattern in G8B10B mode. The received data is good but the ls_sync singal never goes high. What am doing wrong?
The G8B10B mode uses GigaBit Ethernet LSM(Link State Machine). Continous K character BC will not be recognized by the GigaBit Ethernet LSM. Use Dynamic mode and external LSM for your specific application. Refer to technical note, LatticeECP2/M ...
988 - How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML input)?
LVPECL (low-voltage, positive emitter coupled logic) has about a 1.8V common-mode. This can only be made compatible with the 1.2V bias of the LatticeSC CML (common mode logic) by adding AC-coupling to remove the DC-bias of the clock source. This can ...
1567 - In LatticeECP3, is it possible to change the serdes mode from 8b/10b to 10b serdes mode via the SCI on the fly when the data rates are same for both mode?
If all control registers bits setting are correct for both modes, it will work. To get the control registers bit setting information for each mode, you can use ORCAstra. You will have to apply reset after changing the mode.
968 - Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?
In a LatticeECP2M design, you can re-program the PCS for different CPRI rates using the SCI intertace without having to re-gerneate the PCS in IPexpress. In fact, this is what the current CPRI demo does (supports 3 rates via SCI register access). ...
357 - Is is OK to terminate VCCIB/VCCOB (VDDIB/VDDOB) to power on unused SERDES channels of all Lattice SERDES/PCS based devices (LatticeECP2M / LatticeECP3 / LatticeSC/M)?
As per Lattice Technical Note TN1144, VCCIB and VCCOB are only used to supply input/output termination voltage to match the tranmission lines. By default, if a channel is unused during the IPexpress PCS generation phase, the autoconfig file (.txt) ...
356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?
You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode. The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function ...
355 - What's the best, first step to debug looped-back 16-bit data with 8b10b encoding for SERDES/PCS applications in Lattice FPGA's?
For this type of SERDES application, the 8-bit comma character will always occur in the same 8-bit word location in the 16-bit RX data, as long as the transmitter never sends back-to-back commas or sends commas that are an odd number of cycles apart. ...
354 - Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?
For more background on 16/20 bit mode byte shifting, please refer to FAQ 355. The principles of byte shifting in 16/20-bit mode apply to the LatticeSC , LatticeECP3 and LatticeECP2M PCS blocks in 16/20 bit data mode. The following Verilog general ...
351 - How do the VCCIB pins on the LatticeECP3 need to be connected if the SERDES receive inputs (HDIN) are not being used?
If the SERDES receive input (HDIN) signals are not being used, you have the following options for connecting VCCIB: The LatticeECP3 SERDES input block can be powered down. When the SERDES input logic is not powered it is not necessary to connect the ...
344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?
The answer depends both on device family and data rate: In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP. In the case of the LatticeECP2M and LatticeECP3 devices, the use of the hard PCS CTC depends on the ...
266 - What is the meaning of "ff_rxiclk_ch0" and "ff_ebrd_clk_0" and how to connect them in HD-SDI mode?
A1 : The clock "ff_ebrd_clk_0" is the read clock of the Elastic Buffer in PCS. The clock "ff_rxiclk_ch0" is the read clock of the Down Sample FIFO in PCS. A2 : In HD-SDI mode, the CTC is bypassed, so "ff_ebrd_clk_0" could be connected to '0'; the ...
143 - What is a Digital CDR? How is it different from a normal CDR?
The Lattice High-Value FPGAs with SERDES devices utilize a Digital Clock-Data Recovery (CDR). A Digital CDR is similar to an analog CDR in that it recovers a clock from the data stream and aligns a phase of that clock to correctly sample the data. ...
768 - Can SERDES use different configurations and different reference clock frequencies to support the same data rate?
Yes. Here we are using 300Mbps as an example. When in 10-bit SERDES Only mode, the reference clock frequency (Fref) can be either 30MHz or 60MHz to support 300Mbps data rate. Any of the following configuration settings can be used to support 300Mbps ...
130 - When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?
The dedicated SERDES reference clock inputs for the LatticeECP3 include default ac-coupling capacitors and optional dc-coupled connections. This dc-coupled connection is available only in the case where an external ac-coupling capacitor is being ...
766 - SERDES can run at either full-data-rate mode or half-data-rate mode What is the difference between the two?
With the same reference clock frequency, if the SERDES is configured to half-data-rate mode, the SERDES data rate is only half of the data rate supported in the full-data-rate mode. It is useful when different rates are used for different channels in ...
81 - How long does it take for the SerDes TX PLL to lock?
For both LatticeECP2M and LatticeECP3, the SerDes TX PLL Lock time depends on the value of PLL_LOL_SET and the quality of the TX reference clock (REFCLK). The times given below are measured from release of Quad Reset assuming that REFCLK is stable. ...
1855 - LatticeECP3: What is the recommended cable length for a CAT-6 cable that can be used with SERDES (Serializer/De-Serializer) transmit and receive data at a maximum speed of 3.125Gbps?
The recommended length of CAT-6 cable that can be supported with a SERDES is 10 feet. For more information, please refer to FPGA-TN-02196 (Transmission of High-Speed Serial Signals over Common Cable Media) for more information.
1890 - LatticeECP3: The Lattice SerDeS-based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?
Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...
2391 - LatticeECP3: Please provide pre-emphasis characteristics data for LatticeECP3 SERDES.
Description: We listed various pre-emphasis values in a table with the related parameter "TX_PRE[4:0]". You may get more detail about "TX_PRE[4:0]" from "CHn_TX_PRE" in "LatticeECP3 SERDES/PCS Usage Guide", FPGA-TN-02190. The document FPGA-TN-02190 ...
5541 - LatticeECP5: Can the Clock Tolerance Compensation (CTC) can be modified in PCS IP?
Description: The PCS IP fixed the CTC FIFO setting depending on the Protocol used. Customer can access to modify the code for it is not encrypted. Lattice strongly recommended customers not to modify the CTC as it is set to work as-is and modifying ...
2367 - LatticeECP3: How does the RX loss of signal detection circuitry in the LatticeECP3 SERDES/PCS react to a constant value or a drop in signal condition on the
SERDES serial inputs?
Description: The following sections describe how the LatticeECP3 SERDES/PCS RX loss of signal (LOS) detection circuitry works. Operation: The RX LOS detection circuitry detects the voltage swing on the HDINP/N pins as shown in the "Loss of Signal" ...
2321 - ECP3: In LatticeECP3, can I use the receiver for 2.97Gbps HDMI and the transmitter for 3G SDI(or HD_SDI) in the same channel?
It is possible. In the IPexpress GUI, select SDI as the protocol. User can use 148.5MHz for the reference clock with reference clock multiplier 20x. The source may be either external (dedicated refclk pins) or internal (FPGA core routing clock from ...
1770 - LatticeECP3: Are there any special considerations to interface the LatticeECP3 SERDES to standard SFP transceiver modules?
Referring to the Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA), the LatticeECP3 SERDES inputs and outputs are compatible with the specification. This allows for a very clean interface between the module and the fpga. The ...
2245 - Lattice ECP3: Is it OK to loop XAUI data from the RX XGMII to TX XGMII if the IPG is always between 5 and 8 bytes long?
Description:The IEEE 802.3ae Specification explains that it is possible for a 12 bytes IPG (Inter Packet Gap) to shrink to 5 bytes by the time it reaches the RX XGMII interface. This is due to many factors, including clock rate compensation. ...
1739 - LatticeECP3 : What are the functions of register bits tdrv_drvcur_set and tdrv_amp_boost?
The register bits of LatticeECP3 tdrv_drvcur_set and tdrv_amp_boost are used to control SERDES differential output voltage. The register bit tdrv_drvcur_set sets the reference current of SERDES transmit driver. The register bit tdrv_amp_boost is used ...
833 - Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?
Lattice Diamond: ECP2M: PCS: Yes, you can control where an LatticeECP2M (Physical Coding Sublayer) PCS block is located. The PCS blocks on an LatticeECP2M device can be located at either the upper right, upper left, lower right or lower left. These ...
6020 - ECP5: Is SSC input supported in ECP5?
Solution: Yes, our ECP5 supporst SSC. Please refer to TN1261(ECP5 and ECP5-5G SERDES/PCS Usage Guide) for the details on the section as: Spread Spectrum Clocking (SSC) Support
1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a
bitstream file to perform equalization series loopback without modifying
my core design or re-generating SERDES/PCS module from IPExpress?
For LatticeECP3 device, we provide equalization series loopback for system debug. The equalization series loopback means that the data from high speed input pins (HDINP/N) serially loopback to high speed output pins (HDOUTP/N) via equalization ...
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