It is possible. In the IPexpress GUI, select SDI as the protocol. User can use 148.5MHz for the reference clock with reference clock multiplier 20x. The source may be either external (dedicated refclk pins) or internal (FPGA core routing clock from PCLK pins).
For HD_SDI mode at transmitter, the user should select 'div2' in tx rate mode in the GUI.
Switching to HD_SDI(1.485Gpbs) on the fly also can be done by writing '1' into the RATE_MODE_TX bit(CH_14[1]) via SCI interface. In this case the tx must go through reset sequence. For more information, refer to the LatticeECP3 SERDES/PCS Usage Guide, FPGA-TN-02190.