SERDES
7337 - Avant-G/Avant-X: What is the max peak-to-peak voltage of differential refclk for SERDES?
The max peak-to-peak input voltage of the differential reference clock for Avant-G and Avant-X is 1.15V, with a minimum = -0.3V.
1691 - LatticeECP3: Can LatticeECP3 support OC3/OC12/OC48 SONET/SDH framer or mapper applications?
LatticeECP3 has SERDES block that can run in simple 8-bit-only mode to support SDH/SONET (Synchronous Digital Hierarchy/ Synchronous Optical Networking) framer and mapper applications. System requirement might provide some flexibility. There are ...
1690 - LatticeECP3: What are minimum and maximum voltage levels of SERDES inputs?
You may refer to Table 3-9 (Serial Input Data Specifications) of LatticeECP3 Family data sheet. The minimum and maximum voltage levels of LatticeECP3 SERDES inputs are defined as input levels (VRX-IN) in LatticeECP3 data sheet. The minimum input ...
2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?
The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...
6769 - MPCS IP: Why does the settings written to the PMA registers does not reflect to the actual signal?
To update any PMA settings in the device, the REG80 need to be set.
5923 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Can the DSI to CMOS IP be changed to DPHY1 from DPHY0?
The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...
7022 - CertusPro-NX/MPCS: Does the MPCS IP GUI for CertusPro-NX has a way to validate if the FVCO (VCO frequency) is within the SerDes specification limit?
Solution: The MPCS IP has an update that added the FVCO checker. It is available on Radiant 2023.2 or later. In case the user cannot upgrade to the said version, kindly file techsupport ticket to have an appropriate software patch. ...
5824 - [ECP5/ECP5-5G] How to select DCU and Channel in SCI?
The user need to use these pins (sci_en_dual, sci_en, and sci_sel) to select the DCU and Channel need to access.
1527 - LatticeECP3: Why is the SERDES Quad C powered by VCCIB instead of supplying 1.2v, or 1.5v with passive filtering?
The SERDES Quad C of LatticeECP3 FPGA on the Video Protocol board is reserved for HDMI/DVI interface. The HDMI/DVI interface is using TMDS signaling which has a common mode voltage around 3V and a differential swing range of 400-600mV. In order for ...
214 - PCS Simulation: Iteration Limit Error
Description: An iteration limit error may appear when simulating using the PCS IP core. Solution: There are several possible causes for the Iteration Limit Errors. The polarities of the PCS resets are incorrect. When the SERDES Quad reset is removed, ...
6466 - MPCS IP: Can the equalization algorithm of the MPCS IP module be selected through the LMMI dynamically?
This can be done dynamically using LMMI (Lattice Memory Mapped Interface). The user just has to write the register address value (‘d217) to the lmmi_offset_i (address/offset) to access that PMA register. The needed information are shown below: ...
6924 - SerDes/PCS for ECP5/ECP5-5G: Why is TX-to-RX Serial Loopback not available in SerDes/PCS?
The loopback mode is not a static setting, but rather is dynamically controlled through the SCI Interface using the SerDes Control Register 6 (CH_15) > lb_ctl[3:0]. Please refer to Appendix A. Configuration Registers > Per Channel SerDes Control ...
1959 - [LatticeECP2/M] Can the SERDES input voltage threshold be modified to force the SERDES into a reset state?
The SERDES input voltage threshold cannot be modified. But you can adjust the SERDES register RLOS_HSET(increase or reduce the threshold) which is described on page 72 of the LatticeECP2M SERDES/PCS Usage Guide, TN1124 If the SERDES input voltage is ...
6095 - ECP5/ECP5-5G / SERDES / PCS / PCIe: How to stabilize ECP5 SerDes/PCS-based design with unexpected behaviors (ex: Receiver CDR failing to lock & receiver data is unstable) that happened on PCIe/g8B10B/SGMII/SDI interfaces?
Description:This articles shows details and workaround to stabilize ECP5 SerDes/PCS-based design with unexpected behaviors. Solution:This is a known issue for Lattice ECP5 (LFE5UM) due to unstable Reset Soft Logic. A documented workaround ...
6446 - CertusPro-NX SERDES: Should the unused channel/s on a SerDes Quad be powered?
Solution: The only requirement is to power-up the channel 1 of the used quad even if this channel is unused. The rest of the unused channel/s can be left floating or not connected. Refer to Section 13.5 of the CertusPro-NX SerDes/PCS User Guide ...