6095 - ECP5/ECP5-5G / SERDES / PCS / PCIe: How to stabilize ECP5 SerDes/PCS-based design with unexpected behaviors (ex: Receiver CDR failing to lock & receiver data is unstable) that happened on PCIe/g8B10B/SGMII/SDI interfaces?

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• 344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

  The answer depends both on device family and data rate: In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP. In the case of the LatticeECP2M and LatticeECP3 devices, the use of the hard PCS CTC depends on the ...

• 143 - What is a Digital CDR? How is it different from a normal CDR?

  The Lattice High-Value FPGAs with SERDES devices utilize a Digital Clock-Data Recovery (CDR). A Digital CDR is similar to an analog CDR in that it recovers a clock from the data stream and aligns a phase of that clock to correctly sample the data. ...

• 697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

  When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...

• 356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

  You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode. The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function ...

• 2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

  The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...