7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

For ECP3, the recommendations for SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination.

Refer to the Electrical Recommendations for Lattice SerDes (FPGA-TN-02077).

When HCSL driver, it depends on the HCSL types (traditional HCSL, Low Power HCSL).

a) Traditional HCSL

i) Popular due to PCIe's use for Refclk.

ii) Add 50-ohm to ground external termination close to the FPGA's RefclkP and RefclkN input pins.

iii) Disable FPGA refclk internal 100-ohm termination (two 50-ohm across the pair).

iv) Can work with either internal AC coupling enabled or not.

b) Low Power HCSL

i) OK to use, but not as popular yet as regular HCSL.

ii) Disable FPGA refclk internal 100-ohm (two 50-ohm across the pair).

iii) Add 0201 size series resistors at outputs of HCSL-LP oscillator (series resistance = 50 - oscillator output Z in its data sheet).

To disable refclk internal 100-ohm termination resistor when using ECP3 PCIe Endpoint core, the pcs_pipe_8b_x1.txt file generated by the PCIe Endpoint core has parameter PLL_TERM (default is 50-ohm). 

PLL_TERM                "50"

PLL_TERM is the parameter to adjust the TX PLL RefClk internal termination.

Set to 50 for internal termination (no termination on the PCB).

   or 

Set to 2K to disable internal termination (because there is termination on the PCB).

Documentation for reference: LatticeECP3 SERDES/PCS User Guide (FPGA-TN-02190)

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