7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

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  Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...

• 988 - How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML input)?

  LVPECL (low-voltage, positive emitter coupled logic) has about a 1.8V common-mode. This can only be made compatible with the 1.2V bias of the LatticeSC CML (common mode logic) by adding AC-coupling to remove the DC-bias of the clock source. This can ...

• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...