1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?
Description:
The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a routing nightmare for the board layout engineer. This topic provides two features of the Lattice PCIe IP which can assist the FPGA designer and board layout engineer in selecting a pinout that works.
Polarity Inversion
The PCIe physical layer provides the ability for polarity inversion. Polarity inversion is when the receive signal can be identified as being inverted and the physical layer can correct the inversion before sending the data to the data link layer. This feature of the PCIe Spec can be used to provide flexibility in the board layout. The P signal is not required to go to the P lane. It may be easier to route the N signal to the P lane. In this case the polarity inversion of the physical layer will correctly handle the signal. This feature is completely automated by the PCIe IP core so if the board layout engineer connects the signals inverted the FPGA designer does not need to do anything special.
Lane Reversal
The Lattice PCIe IP provides the ability for lane reversal (flip_lanes). Lane reversal is when in a multi lane link the Nth lane is connected to lane 0 and lane 0 is connected to the Nth lane. For example, lane 0 -> lane 3, lane 1 -> lane 2, etc. The Lattice PCIe IP provides this feature to assist in the board layout. The PCIe endpoint card specification has a fixed layout of the lanes which goes from lane 0 to lane N. Depending on the package selected and if the device is mounted on the "B" side or "A" side of the board will either provide a layout which matches or creates a twist in the routing. A twist in the high speed serial routing is not recommended, so a better solution is to reverse the lanes. Using the port "flip_lanes" on the PCIe IP the user can control whether the lanes will be flipped or connected directly. The board layout engineer needs to understand when the lanes will be flipped so lane 0 can be connected to lane N, etc.