6056 - ECP5/ECP5-5G: What speeds/data rates does the PCIe and PCIe-5G Endpoint IP support?

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• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

  The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts. This number of MSI interrupts available for the user can be checked in 'Multiple Message ...

• 3674 - LatticeECP2/ECP3: In Peripheral Component Interconnect Express (PCIe), when an endpoint is in the process of transmitting data to the Root Complex, is the endpoint allowed to send a parallel interrupt?

  Description: Yes, when a transaction is in progress from an endpoint of PCIe IP core to the Root Complex, the endpoint can raise a parallel interrupt. However, the interrupt raised by the endpoint is kept in queue and will be processed after ...

• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.