1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

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• 1813 - [PCI Express Endpoint Core]: Why does the Lattice PCI Express X1 Downgrade core that I generated have all channels in the pcs_pipe_8b_xX.txt enabled?

  The Lattice PCI Express X1 Downgrade Core is the same as the X4 Native core with the only difference being the value of the MaxLinkWidth field in the LinkCapabilitiesRegister. Although all channels of the SERDES are enabled in the text file as well ...

• 2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

  Version 5.2 of the Lattice PCI Express IP includes an update to use the reset sequence (instead of the 4ms reset timer) requiring the reference clock from the SERDES to be enabled to the fabric. You likely use a .txt file from an earlier version ...

• 4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

  Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...

• 1102 - All FPGAs: Does Lattice PCIe IP support SERDES pins polarity inversion and PCIe lanes reversal?

  Description: The PCIe specification provides a dedicated layout of the PCIe lanes on the connector. Due to the fixed location of the SERDES pins on Lattice device packages aligning package pins to PCIe lanes can either work perfectly or create a ...

• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...