1890 - LatticeECP3: The Lattice SerDeS-based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?
Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another source is coming from the FPGA fabric(typically from the primary clock spine). This option provides users the flexibility for system design and implementation.
The reference clock source that comes from the FPGA fabric, can come from either a generic FPGA single-ended input or differential LVDS or LVPECL inputs, a PLL or clock divider, or even a gated clock generated from the FPGA logics. Therefore, it does provide users with a lot more flexibility for clock manipulation.
As a result, since this clock can be shared with other FPGA cloud logic that might share other clock domains, its system performance result yields a higher jitter level than the dedicated CML reference clock port. Naturally, the dedicated CML input reference clock pin yields the best system clock quality for possible system performance results. Note that the trade-off to use the dedicated CML input reference clock is less system flexibility and fixed frequency per system requirement. Any clock division or multiplication has to be done outside of the FPGA device.