6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?

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• 1890 - LatticeECP3: The Lattice SerDeS-based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?

  Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...

• 766 - SERDES can run at either full-data-rate mode or half-data-rate mode What is the difference between the two?

  With the same reference clock frequency, if the SERDES is configured to half-data-rate mode, the SERDES data rate is only half of the data rate supported in the full-data-rate mode. It is useful when different rates are used for different channels in ...

• 968 - Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?

  In a LatticeECP2M design, you can re-program the PCS for different CPRI rates using the SCI intertace without having to re-gerneate the PCS in IPexpress. In fact, this is what the current CPRI demo does (supports 3 rates via SCI register access). ...

• 1180 - While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?

  It takes time even in an RTL simulation for the PLL models to lock to the reference clock. Please run the PCS simulation for about 100us. The PLL clocks will dynamically change until the PLL locks to the reference clock.

• 768 - Can SERDES use different configurations and different reference clock frequencies to support the same data rate?

  Yes. Here we are using 300Mbps as an example. When in 10-bit SERDES Only mode, the reference clock frequency (Fref) can be either 30MHz or 60MHz to support 300Mbps data rate. Any of the following configuration settings can be used to support 300Mbps ...