1180 - While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?
It takes time even in an RTL simulation for the PLL models to lock to the reference clock.
Please run the PCS simulation for about 100us. The PLL clocks will dynamically change until the PLL locks to the reference clock.
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