1180 - While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?
1180 - While simulating the LatticeSC/M, LatticeECP2M or LattieECP3 SERDES/PCS QUADS, why aren't the PCS transmit output clocks frequency locked to the SERDES reference clock?
It takes time even in an RTL simulation for the PLL models to lock to the reference clock.
Please run the PCS simulation for about 100us. The PLL clocks will dynamically change until the PLL locks to the reference clock.
Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...
The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode. The assumption is that you are coding your own RTL 8b10b decoder in the fabric. Based on the definition of 8b10b codes , DATA=0x00 ...
Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...
For ECP3, the recommendations for SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. Refer to the Electrical Recommendations for Lattice SerDes ...
LVPECL (low-voltage, positive emitter coupled logic) has about a 1.8V common-mode. This can only be made compatible with the 1.2V bias of the LatticeSC CML (common mode logic) by adding AC-coupling to remove the DC-bias of the clock source. This can ...