1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode.

The assumption is that you are coding your own RTL 8b10b decoder in the fabric.

Based on the definition of 8b10b codes , DATA=0x00 for example is encoded as hex value of 0x274 , or a 10-bit sequence abcdeifrgj=10_0111_0100.

In 10-bit SERDES only mode , the encoded 8b10b 10-bit data appears on the PCS RXD/TXD [9:0] bus such that j is mapped to bit 9 and a is mapped to bit 0 of the bus.

You can perform word alignment to Comma characters either in the PCS/SERDES QUAD or using an external word aligner in the FPGA.

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1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

Related Articles

2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

354 - Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?

355 - What's the best, first step to debug looped-back 16-bit data with 8b10b encoding for SERDES/PCS applications in Lattice FPGA's?