356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode.

The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function as ffc_enable_cgalign_ch0 in LatticeECP2M) signal enables the word aligner to hunt for and lock to a new comma.

The signals above the "WORD ALIGNER" label are FPGA interface signals, whereas all signals below this label are internal to the PCS core.

In an 8b10b mode, Code Violations (rx_cv_detect_[0-3]) appear before the word_align_en_[0-3] pulse and disappear after the pulse once the word aligner has locked to a comma boundary ...

In 10-bit SERDES only mode, the CV signal is not useful, so the only indicator that the word alignment is successful is a correct COMMA 10-bit sequence at the receive FPGA/PCS 10-bit data interface on RXD...

Please refer to the applicable PCS/SERDES technical note user guide or data sheet for information on how to configure the PCS/SERDES for external word alignment control.

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356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

Related Articles

697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

991 - In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?

980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

6095 - ECP5/ECP5-5G / SERDES / PCS / PCIe: How to stabilize ECP5 SerDes/PCS-based design with unexpected behaviors (ex: Receiver CDR failing to lock &amp; receiver data is unstable) that happened on PCIe/g8B10B/SGMII/SDI interfaces?

6095 - ECP5/ECP5-5G / SERDES / PCS / PCIe: How to stabilize ECP5 SerDes/PCS-based design with unexpected behaviors (ex: Receiver CDR failing to lock & receiver data is unstable) that happened on PCIe/g8B10B/SGMII/SDI interfaces?