991 - In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?

When attribute CHx_COMMA_ALIGN is set to "DYNAMIC", the protocol specific Link State Machines are bypassed. In that case, the word aligner will lock alignment (it will stop comparing the incoming data to the user-defined word alignment characters and will maintain current alignment) on the first successful compare to either the first or second user-defined word alignment character after ffc_enable_cgalign_ch(0-3) is pulsed low for at least one clock cycle. Any subsequent low pulse on the ffc_enable_cgalign_ch(0-3) port at the FPGA interface will unlock the word aligner. The word aligner will then re-lock on the next match to one of the user-defined word alignment characters. If desired, ffc_enable_cgalign_ch(0-3) can be controlled by a Link State Machine implemented
externally to the PCS quad to allow a change in word alignment only under specific conditions.

Note: ffc_enable_cgalign_ch(0-3) is active high signal! After it's first successful hunt, this signal can be left steady high or low. When the next word hunt is needed, this signal needs to stay in low state for minimum one clock cycle and then go high in order to start new word hunt.

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356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?
You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode. The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function ...
1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?
The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode. The assumption is that you are coding your own RTL 8b10b decoder in the fabric. Based on the definition of 8b10b codes , DATA=0x00 ...
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In the case of LatticeECP2M/LatticeECP3/LatticeSC/M SERDES/PCS QUADs, logic in the Link State Machine block generates the lsm_status*/ffs_ls_sync_status* signal. This logic is synchronous to the RX recovered clock. A single stage sync flop is OK to ...
1833 - LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?
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1601 - In Lattice ECP2M SerDes, I use continuous K character, BC as the training pattern in G8B10B mode. The received data is good but the ls_sync singal never goes high. What am doing wrong?
The G8B10B mode uses GigaBit Ethernet LSM(Link State Machine). Continous K character BC will not be recognized by the GigaBit Ethernet LSM. Use Dynamic mode and external LSM for your specific application. Refer to technical note, LatticeECP2/M ...

991 - In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?

991 - In LatticeECP2M external LSM mode, how does the word aligner hunt for comma during word alignment?

Related Articles

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

1833 - LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?

1601 - In Lattice ECP2M SerDes, I use continuous K character, BC as the training pattern in G8B10B mode. The received data is good but the ls_sync singal never goes high. What am doing wrong?

1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?