1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

In the case of LatticeECP2M/LatticeECP3/LatticeSC/M SERDES/PCS QUADs, logic in the Link State Machine block generates the lsm_status*/ffs_ls_sync_status* signal. This logic is synchronous to the RX recovered clock. A single stage sync flop is OK to synchronize the signal to the TX clock domain since the lsm_status signal will not have single cycle transitions in most protocols.

For example, in XAUI mode, based on Figure 48 - 7 - PCS synchronization state diagram of the 802.3ae-2002 IEEE specification, the LSM circuitry will not set lsm_status high until it has received at least 4 Comma characters.

So the lsm_status will be low for at least 4 cycles (more than that knowing that Comma columns don't typically occur back to back in a randomized A K R Idle period).

When lsm_status is high, the LSM circuitry will not set lsm_status low until it has received at least 4 consecutive invalid characters. So the lsm_status will be high for at least 4 cycles.

Since lsm_status is high/low for more than one byte clock (or until RX lane RESET is asserted) as per the explanation above, it is not possible to miss a transition on the signal.

Related Articles
980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?
Definition: The GbE Link State Machine (LSM) inside the RX side of the PCS monitors the incoming data for COMMA characters. The first time it detects a COMMA character , it assigns an "even" index to the cycle, and expects any new COMMA characters to ...
356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?
You can use the word_align_en_[0-3]/ffc_enable_cgalign_ch[0-3] either in an 8b10b based or 10-bit SERDES only based mode. The simulation waveforms below shows how a low pulse on the word_align_en_0 (LatticeSC/LatticeECP3 signal that has same function ...
354 - Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?
For more background on 16/20 bit mode byte shifting, please refer to FAQ 355. The principles of byte shifting in 16/20-bit mode apply to the LatticeSC , LatticeECP3 and LatticeECP2M PCS blocks in 16/20 bit data mode. The following Verilog general ...
697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?
When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...
1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?
The response applies to the LatticeECP2M/LatticeECP3/LatticeSC/M PCS/SERDES QUADS used in 10-bit RAW SERDES only mode. The assumption is that you are coding your own RTL 8b10b decoder in the fabric. Based on the definition of 8b10b codes , DATA=0x00 ...

1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

Related Articles

980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

354 - Is there a Verilog code example available to illustrate how to use Comma boundaries For SERDES/PCS based devices to correct for 16/20 byte shifting in FPGA Interface RX DATA?

697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?