980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

Definition:

The GbE Link State Machine (LSM) inside the RX side of the PCS monitors the incoming data for COMMA characters. The first time it detects a COMMA character , it assigns an "even" index to the cycle, and expects any new COMMA characters to also appear on an even boundary. If another COMMA appears on an odd index, then this is considered an error and too many COMMAS in the odd index can cause the LSM to lose sync and start looking for new COMMAS again. This behavior conforms to the IEEE 802.3-2002 GbE Link State Machine specification.

As a result, The PCS LSM status output signal (ffs_ls_sync_status_ch[3:0] or lsm_status_[0-3], depending on FPGA device) goes low when the LSM loses sync, and goes back high when the LSM acquires sync again.

The two example below illustrate the difference between a valid and an invalid even boundary COMMA occurence (C=comma, D=data):

1. VALID COMMA SEQUENCE:

INDEX	0	1	2	3	4	5	6	7	8	9	10	11
CHARACTER	C	D	C	D	C	D	D	D	D	D	C	D

2. INVALID COMMA SEQUENCE:

INDEX	0	1	2	3	4	5	6	7	8	9	10	11
CHARACTER	C	D	C	D	C	D	D	D	D	C	D	C

In example 2, The COMMAs on INDEX 9 and 11 are invalid since they do not fall on an even boundary.

Note that you do not need to create your own COMMA indexing transmission sequence if you use the SGMII and Gb Ethernet PCS IP Core (IPUG60) for the LatticeECP2M and LatticeECP3 devices. The IP automatically properly aligns COMMAs during the Idle phase of Ethernet frames transmission.

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980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

Related Articles

697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

1181 - Which clock do I use to sample the lsm_status*/ffs_ls_sync_status* signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?

356 - In Lattice parts with SERDES/PCS, how can I control the word aligner using my own FPGA-based link state machine ?

1179 - When using the Lattice FPGA PCS/SERDES QUADS in 10-bit Raw SERDES mode, how do I do interpret the 10-bit 8b10 encoded RX DATA?

344 - For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

1181 - Which clock do I use to sample the lsm_status/ffs_ls_sync_status signal in PCS/SERDES based devices? Is there a chance I could miss the lsm_status pulse if I use a 16-bit wide PCS/FPGA interface data?