When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data.
During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach invalid values.
When the CDR finally locks , you will not see any more code violations or disparity errors, and the link state machine in the PCS will sync up correctly.
However, the RX FIFO pointers on some channels (for write and read side) may remain in an invalid state and cause corrupt data to show up on the RX FPGA parallel data. That is why you need to assert the RX channel digital reset to initialize the pointers to valid values. This allows correct data to flow out of the RX PCS FPGA interface.
Lattice recommends that you implement the reset sequence state machines described in TN1176 for LatticeECP3, and TN1124 for LatticeECP2M. You can also implement the RX Lane Resynchronization Logic described in TN1145 for LatticeSC. These state machines automatically assert the RX channel digital reset signals (rx_pcs_rst_ch* for LaticeECP3, ffc_lane_rx_rst_ch* for LatticeECP2M and tx_rst* for LatticeSC) after power up or a CDR loss of lock condition.