In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. In this case, the RX input buffer signal is not sampled by the CDR logic.
If the signal to the input buffer is left floating/inactive, it will cause the rx_los_low_ch[3:0]_s signal to go high. As long as you do not include the Lattice SERDES Reset Sequence State Machine in your design, and you do not use the rx_los_low_ch[3:0]_s signal to reset any of your FPGA logic, then the loopback test will run normally.
On the other hand, when you include the Lattice SERDES Reset Sequence State Machine (see "Control Setup" and "RX Reset Sequence" sections of FPGA-TN-02190) in your design, then this logic continuously monitors the rx_los_low_ch[3:0]_s signal and resets the SERDES/PCS RX logic when this signal is high. In this case, you should not expect the loopback function to work correctly when the RX SERDES input is left floating/inactive.