6924 - SerDes/PCS for ECP5/ECP5-5G: Why is TX-to-RX Serial Loopback not available in SerDes/PCS?
The loopback mode is not a static setting, but rather is dynamically controlled through the SCI Interface using the SerDes Control Register 6 (CH_15) > lb_ctl[3:0].
Please refer to Appendix A. Configuration Registers > Per Channel SerDes Control Register Details > SerDes Control Register 6 (CH_15) of FPGA-TN-02206:
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The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...
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For LatticeECP3 device, we provide equalization series loopback for system debug. The equalization series loopback means that the data from high speed input pins (HDINP/N) serially loopback to high speed output pins (HDOUTP/N) via equalization ...