1000 - How can I implement multiple protocols within a PCS quad (Protocol A RX, Protocol B, TX, etc) on ECP2M and ECP3?

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• 697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

  When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...

• 1514 - LatticeSC/M: What effect does a PCS local/remote fault signal to the 10Gb+ Ethernet MAC have on the MAC TX and RX logic?

  Description: The XAUI PCS communicates the local/remote link fault to the MAC via the XGMII RX data/control bus during the IDLE period, as defined by the IEEE specification. No other signals are used to communicate fault signaling. When the RX MAC ...

• 6654 - 10Gb Ethernet PCS IP Core: How to use the data (Tx and Rx) polarity invert function for 10G PCS core?

  There is a PMA register responsible for data polarity inversion that could be written through the APB interface on 10G PCS IP. From Table A.26 of FPGA-TN-02245, look for rx_polinv and tx_polinv where in writing 1 on this register bit will trigger the ...

• 2722 - SERDES/ECP3:Why do I receive data errors when I configure the LatticeECP3 SERDES/PCS in TX-to-RX Serial Loopback Mode?

  The TX-to-RX Serial Loopback Mode is supported in the LatticeECP3 device (see "Control Setup" and "TX-to-RX Serial Loopback Mode" sections of FPGA-TN-02190). In this loopback test mode, the TX output serial data is looped back into the RX SERDES CDR. ...

• 7170 - CertusPro-NX/MPCS: In a multiple lane MPCS-G8b10b design, why does RX lanes shows all zero data?

  Solution: In case encountering this kind of issue the potential workaround is to create multiple single-instance of PCS-G8b10b per channel. If in doubt how to implement this, kindly contact techsupport@latticesemi.com.