1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

For LatticeECP3 device, we provide equalization series loopback for system debug. The equalization series loopback means that the data from high speed input pins (HDINP/N) serially loopback to high speed output pins (HDOUTP/N) via equalization circuit. There is no clock involved in the equalization series loopback. It is widely used in system debug.

In order to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress, you need to do the following two steps:

     Modify the following attribute in the SERDES/PCS configuration txt file to
        CHx_SSLB         "ENABLED_EQ2T"   # where x specifies the SERDES/PCS channel number to perform equalization series loopback.

    Re-generate the bit stream by using the last step "Force One Level" in ispLEVER or Lattice Diamond tools.

With these two steps, your original core design inside FPBA fabric including Place and Route (R&R) is maintained. The only change for new generated bitstream is to perform the equalization series loopback mode for specified SERDES channel.