2684 - DDR3 IP: Why do I have two top-level wrappers inside a DDR3 IP core package generated from IPexpress ? Which one should I use for my design?

The DDR3 IP core package includes two top-level wrapper files in two different places using the same name, ddr3_sdram_mem_top_wrapper.v or .vhd. One of them which is located in the directory "ddr_p_eval\<user_name>\impl" is used solely for the core evaluation purpose. This top-level wrapper file has a reduced size of local side ports to allow the implementation of the core evaluation project to be completed without an error by resizing the local data buses. Since this change affects the local interface accessibility and functionality of the DDR3 core, this wrapper should be used only for the flow and core utilization evaluation. The other wrapper which is located in "ddr_p_eval\<user_name>\src\rtl\top\<device name>" is the regular one and must be used for user designs and any simulation purposes.

Here is the reason why the resized wrapper is necessary. When an IP core is generated, IPexpress generates an evaluation project assigning all the signals for the core and local user interfaces to the I/O pads. Since the number of DDR3 IP’s user interface signals for read and write data buses together is normally more than eight times than that of the DDR3 memory interface, it is impossible for the core to be implemented if the selected target device does not have enough I/O pad resources. To facilitate the core evaluation with smaller package devices, IPexpress inserts dummy termination logic to decrease the I/O pad counts by reducing the local read_data and write_data bus sizes. And the I/O reduced top-level wrapper is located in the directory "ddr_p_eval\<user_name>\impl" as previously described.

You can find this information in the DDR3 IP core user guide (IPUG80.PDF), "Top-level Wrapper File Only for Evaluation Implementation" section.