2174 - LatticeECP3/DDR3 SDRAM Controller: How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?

2174 - LatticeECP3/DDR3 SDRAM Controller: How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?

Integrating multiple DDR3 interfaces into a LatticeECP3 device can be done using one of the following cases depending on the locations of the DDR3 interfaces.

1. When locating all DDR3 interfaces on one side (either the left or right side):
Sharing of a dedicated PLL is needed in the CSM (clock synchronization module) with all DDR3 interfaces on each side. Each side of ECP3 has one or two PLLs that have a direct connection to ECLK. Use only one of those legal PLLs. For this reason, a CSM must be implemented and shared with all DDR3 interfaces in each side of LatticeECP3.

When generating a DDR3 IP core, the core also generates a CSM block and its preference set  are assigned a correct PLL. Only one CSM is required to be shared with all DDR3 interfaces on one side. When instantiating the second DDR3 interface, for example, remove the CSM instantiation from the second DDR3 IP core wrapper and get the connection with the CSM from the first DDR3. An easy way is not to use the DDR3 core wrapper but to instantiate the core directly from your top level.

When the CSM is shared, the DQSDLL update control must be enabled only when both controller are in the idle status. Use a two-input OR gate (or multi-input OR gate if more than two DDR3 interfaces are to be used) to achieve this by connecting the UDDCNTLN signal from each controller to each input of the OR gate and connect the output to the UDDCNTLN input of the CSM.

The wl_rst_datapath signal from the DDR3 core is a DQS circuit reset that is connected to the CSM's reset_datapath input. This signal is asserted when the write leveling process is completed. If not using write-leveling, this signal stays low all the time. The recommended usage for two (or multiple) DDR-PHY integration is to use a 2-input (or multiple input) AND gate. It will ensure two (or more) cores complete the write-leveling process at the same time and each core resets the DQS circuitry only once when the write leveling mode is enabled. For the non-write leveling mode, use either an AND gate or connect the CSM reset_datapath input to the wl_rst_datapath output of any one of the cores.


2. When locating DDR3 interfaces on both sides:
When using both sides for multiple DDR3 interfaces, instantiate a CSM for each side with a corresponding preference sets. This requires two separate CSM preference sets, one for each side. The preference sets can be obtained by the DDR3 IP core generation with the desired locations selected. Follow the single side DDR3 implementation instruction listed above for each side implementation.