5261 - ECP5/ECP5-5G: Does DDR3 SDRAM controller IP support DDR3L?

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  Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...

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• 2174 - LatticeECP3/DDR3 SDRAM Controller: How can I integrate two (or more) DDR3 IP cores into one LatticeECP3 device?

  Integrating multiple DDR3 interfaces into a LatticeECP3 device can be done using one of the following cases depending on the locations of the DDR3 interfaces. 1. When locating all DDR3 interfaces on one side (either the left or right side): Sharing ...

• 2218 - LatticeECP3/DDR3 SDRAM Controller v1.3.0 and up: For DDR3 controller IP core v1.3, why does the simulation result fail while the design works well without a failure on the board?

  The READ_PULSE_TAP handling guideline has been changed for the DDR3 memory controller IP v1.3 core (or later version). READ_PULSE_TAP is a user controlled input to the core to compensate for the DQS round trip delay in a DDR3 memory controller IP ...