7759 - DDR Memory Controller v2.6.0 - Driver API caused invalid training status

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• 1076 - LatticeECP2/XP2: How many DDR memory interfaces can be implemented on a single FPGA device?

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  Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, ...

• 1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?

  LatticeECP3 devices have one DQSDLL per side. DQSDLL has an input port called UDDCNTLN that allows its DLL code value (DQSDEL output) to be updated while it is asserted Low. The updated code value is used to generate precise PVT (Process Voltage ...

• 2087 - LatticeECP3/DDR3: How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?

  The CSM (Clock Synchronization Module) module of the DDR3 memory controller ipcore multiplies the input reference clock frequency four times for the DDR3 bus operations and two times for the local bus operations. This means that the DDR3 IP core uses ...