2474 - LatticeECP3: Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?

2474 - LatticeECP3: Does the DDR2/3 SDRAM Controller IP evaluation design and testbench from IPexpress support SDF timing simulations?

The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers.

As a result, the routing delay from the last flip flop to the IO is large. Since the  simulation testbench drives and monitors these IOs, SDF back annotated simulation won't be able to run at required speed.

Note that the evaluation design does not support gate-level simulation even without SDF, if the number of available IO pads of the target device is less than the number of core user IO's.  This is not a limitation with the IP Core itself. If you integrate the IP Core into your design and remove the user side IO buffers, then you should be able to run SDF back annotated timing simulations at speed.