Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...
The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers. As a result, the routing delay from the last flip flop to the IO is large. Since the simulation testbench drives and monitors these ...
Issue Description/Symptom: The user RTL is unable to write to PCIe Link Layer registers through LMMI when PCIeLL is enabled and accessed on the Hard IP Setup of the Reveal Controller. Figure 1: Root Causes: Reveal will insert a MUX which handles the ...