Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers. As a result, the routing delay from the last flip flop to the IO is large. Since the simulation testbench drives and monitors these ...
The READ_PULSE_TAP handling guideline has been changed for the DDR3 memory controller IP v1.3 core (or later version). READ_PULSE_TAP is a user controlled input to the core to compensate for the DQS round trip delay in a DDR3 memory controller IP ...
Integrating multiple DDR3 interfaces into a LatticeECP3 device can be done using one of the following cases depending on the locations of the DDR3 interfaces. 1. When locating all DDR3 interfaces on one side (either the left or right side): Sharing ...