Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
The DDR2/3 SDRAM Controller IP evaluation reference design from IPexpress maps the IP Core user side IOs to buffers. As a result, the routing delay from the last flip flop to the IO is large. Since the simulation testbench drives and monitors these ...
The READ_PULSE_TAP handling guideline has been changed for the DDR3 memory controller IP v1.3 core (or later version). READ_PULSE_TAP is a user controlled input to the core to compensate for the DQS round trip delay in a DDR3 memory controller IP ...
Description Lattice XO2 and XO3 devices do not natively support the conventional I²C Soft IP provided in Propel. Customers who require I²C functionality must use the reference designs provided by Lattice Semiconductor. To implement I²C communication, ...