2527 - LatticeECP3: Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?

Description:

There are two possibilities:

1. The signal paths in the ignored preferences may not be correct. This usually happens when a user takes the IP core preferences as-is without getting them localized. If there is any added hierarchy, the paths in the original preferences must be updated. For example, let's assume that you have the following form preference generated from IPexpress:

LOCATE PGROUP "clocking/clk_phase/phase_ff_0_inst/clk_phase0" SITE "R32C5D" ;

If there is any hierarchy change, for example another top-level instantiates the core with the name "ddr3", the preference must be updated accordingly as shown below:

LOCATE PGROUP "ddr3/clocking/clk_phase/phase_ff_0_inst/clk_phase0" SITE "R32C5D" ;”

See "Handling DDR3 IP Preferences in User Designs" section in the IP user guide, IPUG80.PDF.

2. The target device may have been changed. If this is the case, a new DDR3 core with the same configuration needs to be regenerated targeting the new device. This is to get the new preference set for the new target device. The location for the example preference varies depending not only on the device but also on the package size. Once you generate a core targeting a right device, you will get the corresponding locations from the generated core LPF. Make sure the DQS pin locations also get updated. Once the new preferences are obtained, their paths can be localized as explained in the #1 case above.

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2527 - LatticeECP3: Some of the DDR3 IP core preferences are being&nbsp;ignored in my design, and I am getting a few timing errors. How can this happen?

2527 - LatticeECP3: Some of the DDR3 IP core preferences are being&nbsp;ignored in my design, and I am getting a few timing errors. How can this happen?

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2527 - LatticeECP3: Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?

2527 - LatticeECP3: Some of the DDR3 IP core preferences are being ignored in my design, and I am getting a few timing errors. How can this happen?

2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?