968 - Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?

In a LatticeECP2M design, you can re-program the PCS for different CPRI rates using the SCI intertace without having to re-gerneate the PCS in IPexpress. In fact, this is what the current CPRI demo does (supports 3 rates via SCI register access).

Note that this is not the case in a LatticeSC flexiPCS, as the register interface cannot change some PLL/CDR attributes. These attributes are configured only once every time the PCS is generated in IPexpress.

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968 - Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?

968 - Do I need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different CPRI data rates. Can I instead re-write PCS registers on the fly to support different CPRI data rates?

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2695 - LatticeECP3:&nbsp; Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

1748 - Common Public Radio Interface - IP Core: Do I need to use a clock cleaner when using CPRI IP core (Common Public Radio Interface) with Lattice SERDES based FPGA?

1723 - CPRI:&nbsp; Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation? &nbsp;

6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?

2695 - LatticeECP3: Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

1723 - CPRI: Can Lattice CPRI IP core (Common Public Radio Interface) support auto-negotiation?