1833 - LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?
Lattice does not have an example 16-bit word alignment code. It is recommended to use the PCS module in IPexpress within the Lattice Diamond software tools to generate the 16-bit word alignment verilog code.
Information about the PCS module and options can be found through the online help in the Lattice Diamond software tools.
- In the main Lattice Diamond window, select:
Help> Lattice Diamond Help
- Select the Search button and enter:
IPexpress PCS module
- For PCS module information specific to the ECP3, select
PCS Options (LatticeECP3)
From within the Lattice Diamond software tool interface, use the IPexpress module to create the Verilog code.
- Select the IPexpress icon or select
Tools> IPexpress
- On the left side of the IPexpress window, select
Module->Architecture_Modules->IO->PCS
- Enter the requested information regarding path, file name, and type of ouput (ex. Verilog), etc
- Select Customize
- A window appears for selecting and specifying all requirements.
- For more information about the choices and settings, select Help in the lower right corner of the PCS window.
- Select
PCS Options (LatticeECP3)
- Scroll down the page to see a description of options for each tab in the PCS module window.
- Go through each tab to select the necessary options for your application.
- Select the Quad tab and set options for the channels in order to be able to set the word alignment options.
- Select the PCS Advanced1 tab to access the options for Word Alignment.
- When all options are specified, select Generate.
- Refer to the Log window to be sure the code was generated succesfully.
More information on the LatticeECP3 SERDES/PCS can be found in
Note: In the process of transmitting and receiving the data, if the 16 bit word alignment does not match the transmitted data (the data becomes misaligned), it may be necessary to correct the alignment. Refer to
FAQ 355.
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