130 - When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?

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• 7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

  For ECP3, the recommendations for the SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. You may refer to the Electrical Recommendations for Lattice ...

• 768 - Can SERDES use different configurations and different reference clock frequencies to support the same data rate?

  Yes. Here we are using 300Mbps as an example. When in 10-bit SERDES Only mode, the reference clock frequency (Fref) can be either 30MHz or 60MHz to support 300Mbps data rate. Any of the following configuration settings can be used to support 300Mbps ...

• 1890 - LatticeECP3: The Lattice SerDeS-based FPGA has two reference clock sources for SERDES. Are there any differences between the dedicated clock input source and the FPGA reference clock source for the SERDES?

  Lattice SerDeS-based FPGA products(such as LatticeECP3 and LatticeSC) in general, provide two choices of reference clock source for the SERDES. One is the dedicated input for the SERDES/PCS block(typically differential CML input pins), and another ...

• 988 - How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML input)?

  LVPECL (low-voltage, positive emitter coupled logic) has about a 1.8V common-mode. This can only be made compatible with the 1.2V bias of the LatticeSC CML (common mode logic) by adding AC-coupling to remove the DC-bias of the clock source. This can ...

• 6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?

  Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...