The Lattice High-Value FPGAs with SERDES devices utilize a Digital Clock-Data Recovery (CDR). A Digital CDR is similar to an analog CDR in that it recovers a clock from the data stream and aligns a phase of that clock to correctly sample the data. The difference is how this is done and its performance.

An analog CDR uses a charge pump and loop filter to control an oscillator. The CDR keeps the recovered clock running at the same frequency as the clock from the extracted data. This is an exact frequency locked clock which is then phase aligned to sample the serial data. Using a loop filter the oscillator can keep the same frequency even when the data does not provide many transitions to update the oscillator.

A Digital CDR is created using completely digital logic. A Digital-to-Analog Converter (DAC) controls the input to the oscillator selecting a specific frequency at which the CDR recovered clock will run. As data transitions come into the CDR this frequency is adjusted to match transitions in the data stream. In the absense of data transitions the CDR will drift back to the DAC value faster compared to an analog CDR loop filter implementation. The benefits of the Digital CDR is that it is physically much smaller, uses less power, and can lock faster to the incoming data stream since the DAC value keeps the oscillator very close to the data frequency.

Lattice chose a Digital CDR for the High-Value FPGA families which target SERDES interfaces utilizing 8b10b encoding or other high transition data formats.  The Digital CDR provides the optimum trade off in cost, power, and performance for these applications.