The Lattice ECP5 cannot support SDI Rx with a pathological pattern and, therefore, is not fully SDI-compliant. We do not recommend using the SDI solution on ECP5 unless the customer only requires SDI Tx.
This article clarifies the clock domain assignments for the MII/GMII interface as described in the Tri-Speed Ethernet IP User Guide (FPGA-IPUG-02084-2.2). The table below includes an amended version of the original documentation to help users ...
The line number and Video Payload Identifier (VPID) bytes are directly extracted from the input video stream. If they are invalid, the extracted line number and VPID will also be invalid. They are not corrected in the IP based on the extracted video ...
Configuration registers of Tri-Speed Ethernet MAC (TSMAC) IP Core can be accessed through Host Interface. Also, values for particular registers can be hard coded in the ts_mac_core.v file if you are not using any host interface module in your design.
The user can change the hardened D-PHY blocks location between DPHY0 and DPHY1 by adding a LOCATE preference in the .lpf file to SITE "MIPIDPHY0" or SITE "MIPIDPHY1". The LOCATE preference is the following, for example: LOCATE COMP " ...