7760 - What are the associated MII/GMII interface clock domains in Tri-Speed Ethernet (TSE) IP v1.7.1 and earlier, and which versions does this apply to?
This article clarifies the clock domain assignments for the MII/GMII interface as described in the Tri-Speed Ethernet IP User Guide (FPGA-IPUG-02084-2.2). The table below includes an amended version of the original documentation to help users correctly interpret the clocking scheme, especially in the context of simplified vs. non-simplified clocking options.
The amendments are highlighted in bold for clarity.
Important: This clarification is only applicable to TSE IP version v1.7.1 or earlier. It does not apply to v2.0.0 and later, as the non-simplified clocking scheme has been deprecated and the related chapters were removed starting from FPGA-IPUG-02084-2.3.
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4.7.1. MII/GMII Interface
The MII/GMII interface is only available if the selected MAC Operating Option is MII/GMII.
Table 4.10. MII/GMII Interface Ports
Port | Clock Domain1 | Direction | Description |
mii_gmii_txd_o[7:0] | txmac_clk_i2
mii_gmii_tx_clk_i3
mii_gmii_gtx_clk_i3
tx_mii_clk_i5 | Output | mii_gmii_txd_o[7:0]—Transmitted data to the PHY Chip in 1G speed.
mii_gmii_txd_o[3:0]—Transmitted data to the PHY Chip in 10M/100M speed, only use low nibble. |
mii_gmii_tx_en_o | | Output | Transmit Data Enable. Asserted by the TSEMAC IP core to indicate the mii_gmii_txd_o bus and mii_gmii_tx_er_o contains valid frame data. |
mii_gmii_tx_er_o | | Output | Transmit Data Error. Asserted when the TSEMAC IP core generates a coding error on the byte currently being transferred. |
mii_gmii_rxd_i[7:0] | rxmac_clk_i2
mii_gmii_rx_clk_i3/4
rx_mii_clk_i5 | Input | mii_gmii_rxd_o[7:0]—Receive data from the PHY Chip in 1G speed
mii_gmii_rxd_o[3:0]—Receive data from the PHY Chip in 10M/100M speed, only use low nibble. |
mii_gmii_rx_dv_i | | Input | Receive Data Valid. Indicates the data on the mii_gmii_rxd_i bus and mii_gmii_rx_er_i signal are valid. |
mii_gmii_rx_er_i | | Input | Receive Data Error. This signal is asserted by the external PHY device when it detects an error during frame reception. |
col_i | Asynchronous | Input | Collision. This active-high signal indicates a collision occurred during transmission. This signal is valid for half-duplex operation in Fast Ethernet (10/100) only. |
crs_i | Asynchronous | Input | Carrier Sense. This signal, when logic high, indicates the network has activity. Otherwise, it indicates the network is idle. This signal is valid for half-duplex operation in Fast Ethernet (10/100) only. |
Notes:
Clock domain varies based on the selected attribute. For more information, refer to the corresponding clock diagram in the Clocking
Non-simplified Clock Scheme— MII/GMII mode, 1G operating rate.
Simplified Clock Scheme— MII/GMII mode, 10M/100M operating rate.
Simplified Clock Scheme—MII/GMII mode, 1G operating rate.
Non-simplified Clock Scheme— MII/GMII mode, 10M/100M operating rate.