1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?
The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached.
- CTC delete-idle function: CTC deletion occurs when the local receive clock is slower than the receive recovered clock. In this circumstance, the CTC FIFO is written faster than it it is read. This will cause the FIFO occupancy to increase and reach the high watermark. It is possible to delete more than one idle-ordered set during the Inter packet Gap (IPG) period. It depends on how large the clock-drift is between read and write clocks when the IPG period arrives. If the drift is less than 2 clock-periods, then one one idle code-group should be deleted. If the clock drift is between 2-to-4 clock periods, then two-consecutive idle code groups should be deleted. And so on. For example, When GMII data rate is 1 Gbps, and the maximum frame size is 1500 bytes,the expected maximum clock slip for +/- 100ppm offset is about 0.2 clock periods per frame. So no more than one idle code group is deleted during the IPG period. However, for Jumbo frames (let's say 15,000 bytes or larger) the clock slip per frame may be 2.0 clocks per frame. So, in this cases, there might be two consecutive idle code groups dropped. When the GMII data rate is 100Mbps or 10Mbps, the clock slips between frames is 10X or 100X larger than that at 1 Gbps. So more consecutive idle ordered sets may be dropped for these data rates. Since the MII is running 10 or 100 times slower than the CTC, the IPG period is 10 or 100 times larger than that of 1 Gbps to accomodate for the larger amount of ordered sets to be dropped.
- CTC insert-idle function: CTC insertion occurs when the local receive clock is faster than the receive recovered clock. In this circumstance, the CTC FIFO is read faster than it is written. This will cause the FIFO occupancy to decrease and reach the low watermark. The CTC logic monitors the FIFO occupancy. If the occupancy drops below the low threshold (for example 16), then the CTC logic starts monitoring the data being read out from the FIFO. When it detects that an IPG region is beginning or is currently in progress, the CTC logic forces the FIFO to stop reading for one idle ordered set duration. During this time, the control logic will insert an idle ordered set in the outbound RX data path. This is called a CTC insert. If the FIFO occupancy is still below the low threshold after the CTC insert has been performed, then the CTC logic will do another consecutive CTC insert. The CTC logic will continue to do consecutive CTC inserts as long as the FIFO occupancy remains below the low FIFO threshold. The number of idle ordered sets inserted depends on the clock-drift between read and write clocks, just as it does in the case of the CTC delete-idle function.