967 - LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?

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  For Avant SGMII, the Rx data path of each port needs 1 PLL for soft CDR, associated with the HPIO of the same bank. As for Tx, a single PLL can be shared across multiple ports. Therefore, for 2 SGMII, the customer needs 2 + 1 = 3 PLL, and for 4 ...

• 6646 - SGMII and Gb Ethernet PCS IP Core: What should be the external PLL clock when using 2 SGMII CDRs?

  The two PLLs REFCLK of SGMII CDR are driven by the dedicated connection from LLC_PLL (Lower Left Corner PLL). Note: Some dedicated GPLL_LLC input clock is reserved for one of the SGMII CDR inputs and cannot be used for the external PLL's REFCLK. ...

• 1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

  The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...

• 980 - GbE PCS: Why does the GbE PCS link state machine status signal regularly pulse low even though the SERDES/PCS receives valid 8b10b encoded characters?

  Definition: The GbE Link State Machine (LSM) inside the RX side of the PCS monitors the incoming data for COMMA characters. The first time it detects a COMMA character , it assigns an "even" index to the cycle, and expects any new COMMA characters to ...

• 2545 - LatticeECP3: Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?

  Description:The Inter Packet Gap (IPG) shrink (deleting of /I2/ ordered set) will always happens as long as there is a PPM (Part per Million) difference between the local reference clock and the remote reference clock, and the remote reference clock ...