7554 - [Avant-E] SGMII and Gb Ethernet PCS IP Core: Can I implement 2 or 4 SGMII with the Avant-E30?

For Avant SGMII, the Rx data path of each port needs 1 PLL for soft CDR, associated with the HPIO of the same bank. As for Tx, a single PLL can be shared across multiple ports.

Therefore, for 2 SGMII, the customer needs 2 + 1 = 3 PLL, and for 4 SGMII, we need 4 + 1 = 5 PLL.

From the Avant-E30 block diagram below, 2 and 4 SGMII can fit in the device, provided the PLLs are not used for other purpose:

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7554 - [Avant-E] SGMII and Gb Ethernet PCS IP Core: Can I implement 2 or 4 SGMII with the Avant-E30?

7554 - [Avant-E] SGMII and Gb Ethernet PCS IP Core: Can I implement 2 or 4 SGMII with the Avant-E30?

Related Articles

967 - LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?

1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

6646 - SGMII and Gb Ethernet PCS IP Core: What should be the external PLL clock when using 2 SGMII CDRs?

7747 - Avant: DDR Memory Controller Revision and Migration Guide

7350 - Avant-X 25G Ethernet: Why does Lattice Radiant Software show a critical warning when designing the 25G Ethernet IP on Avant-X FPGA with -2 and -1 performance grades?