6646 - SGMII and Gb Ethernet PCS IP Core: What should be the external PLL clock when using 2 SGMII CDRs?

6646 - SGMII and Gb Ethernet PCS IP Core: What should be the external PLL clock when using 2 SGMII CDRs?

The two PLLs REFCLK of SGMII CDR are driven by the dedicated connection from LLC_PLL (Lower Left Corner PLL).

Note: Some dedicated GPLL_LLC input clock is reserved for one of the SGMII CDR inputs and cannot be used for the external PLL's REFCLK. Forcing to use this will result in a placement error during Place & Route.
For example in 484 BGA, 'T2' is reserved for SGMII CDR1's input.