6646 - SGMII and Gb Ethernet PCS IP Core: What should be the external PLL clock when using 2 SGMII CDRs?

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• 1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

  The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...

• 967 - LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?

  The SGMII and Gb Ethernet PCS IP "xmit_autoneg" signal does not have the same definition as the xmit variable defined by the 802.3 spec. The 802.3 spec uses the xmit variable to indicate CONFIGURATION (/C/) IDLE (/I/) or Data condition for transmit ...

• 7554 - [Avant-E] SGMII and Gb Ethernet PCS IP Core: Can I implement 2 or 4 SGMII with the Avant-E30?

  For Avant SGMII, the Rx data path of each port needs 1 PLL for soft CDR, associated with the HPIO of the same bank. As for Tx, a single PLL can be shared across multiple ports. Therefore, for 2 SGMII, the customer needs 2 + 1 = 3 PLL, and for 4 ...

• 2545 - LatticeECP3: Why does the SGMII and Gb Ethernet PCS IP reduce the Inter Packet Gap between Ethernet frames?

  Description:The Inter Packet Gap (IPG) shrink (deleting of /I2/ ordered set) will always happens as long as there is a PPM (Part per Million) difference between the local reference clock and the remote reference clock, and the remote reference clock ...

• 2695 - LatticeECP3:  Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

  The LatticeECP3 2.5 GBE MAC and PCS IPs described in IPUG98 and IPUG99, will run at 1.25 Gbps by changing the ref_clk clock source to 125 Mhz as shown in the "PHY with Host Bus Control Interface" figure of IPUG99. The byte_clk and word_clk will be ...