3524 - Lattice ECP3: How can we access configuration registers of Lattice Tri-Speed Ethernet MAC (TSMAC) IP Core ?

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• 1515 - LatticeECP3: Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC framer and processor core?

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• 7760 - What are the associated MII/GMII interface clock domains in Tri-Speed Ethernet (TSE) IP v1.7.1 and earlier, and which versions does this apply to?

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• 2695 - LatticeECP3:  Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

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• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...