2324 - [LatticeECP3]: Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?

2324 - [LatticeECP3]: Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?

If the user is using a Lattice DDR3 memory controller IP core version 1.2 or later, the user can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed 1:2:4 ratio of clocks among the reference clock input (clk_in), system clock (sclk) and the DDR3 clock (eclk), respectively. The newer version CSM in the v1.2 or later supports variable clock ratios between the input reference clock and the system clock. The ratio between the system clock and the DDR3 clock must remain in 1:2 ratio. If the user use a 75MHz input reference clock for 400MHz DDR3 operations, for example, the supported clock ratio becomes 75MHz(clk_in) : 200MHz(sclk) : 400MHz(eclk). Note that the CSM from the generated DDR3 IP core has the 1:2:4 ratio by default, and the user will need to regenerate the PLL module to provide the desired clock ratio.