768 - Can SERDES use different configurations and different reference clock frequencies to support the same data rate?

• Related Articles

• 766 - SERDES can run at either full-data-rate mode or half-data-rate mode What is the difference between the two?

  With the same reference clock frequency, if the SERDES is configured to half-data-rate mode, the SERDES data rate is only half of the data rate supported in the full-data-rate mode. It is useful when different rates are used for different channels in ...

• 2324 - [LatticeECP3]: Can I use a different rate of the input reference clock other than 100MHz when a 400MHz/800Mbps DDR3 interface is implemented?

  If the user is using a Lattice DDR3 memory controller IP core version 1.2 or later, the user can use a different rate of input reference clock. The original clock synchronization module (CSM) in the earlier version DDR3 IP cores require the fixed ...

• 6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?

  Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...

• 7762 - PCIe: Does Lattice ECP3 Serdes reference clock compatible with HCSL driver?

  For ECP3, the recommendations for the SerDes Reference Clock Interface are based on the LVDS and LVPECL standards and these are guaranteed to have no issues with the 100-ohm termination. You may refer to the Electrical Recommendations for Lattice ...

• 130 - When is it appropriate to use dc-coupling with the LatticeECP3 SERDES reference clock?

  The dedicated SERDES reference clock inputs for the LatticeECP3 include default ac-coupling capacitors and optional dc-coupled connections. This dc-coupled connection is available only in the case where an external ac-coupling capacitor is being ...