6466 - MPCS IP: Can the equalization algorithm of the MPCS IP module be selected through the LMMI dynamically?

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• 6977 - [CertusPro-NX] Serdes/PCS: Why does the MPCS-8b10b IP fails in x8 lane simulation?

  Solution: The issue has been fixed in Radiant 2023.2 (MPCS IP version 1.4.2 or later).

• 7022 - CertusPro-NX/MPCS: Does the MPCS IP GUI for CertusPro-NX has a way to validate if the FVCO (VCO frequency) is within the SerDes specification limit?

  Solution: The MPCS IP has an update that added the FVCO checker. It is available on Radiant 2023.2 or later. In case the user cannot upgrade to the said version, kindly file techsupport ticket to have an appropriate software patch. ...

• 6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

  Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...

• 1693 - LatticeECP3: When I do system debug with LatticeECP3 device, how can I generate a bitstream file to perform equalization series loopback without modifying my core design or re-generating SERDES/PCS module from IPExpress?

  For LatticeECP3 device, we provide equalization series loopback for system debug. The equalization series loopback means that the data from high speed input pins (HDINP/N) serially loopback to high speed output pins (HDOUTP/N) via equalization ...

• 6233 - SLVS-EC Receiver IP Core: How to Set Reference Clock Frequency of SLVS-EC Rx IP core?

  The “reference clock” corresponds to the IP port refclk_*. This port represents the differential clock of the internal MPCS PLL. It can be sourced from any clock signal capable of generating the MPCS clock frequency specified in the “MPCS Clock ...