6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible as this info is needed during IP generation so the PCIe soft RTL will know how to expose the interface at top level.

Related Articles
PCIe DMA in Ring Buffer Operation mode unable to be stopped
Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...
7192 - PCIe for Nexus FPGAs: Why do PCIe Configuration Space registers (i.e. Device ID, Vendor ID, etc) not persist after first enumeration?
Description: The PCIe IP v1.1 contains a bug in which the Device ID and Vendor ID values in the GUI do not reflect in the configuration space. Solution: As a workaround, users could configure the IDs in respective registers. This is done through the ...
DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval
Description DisplayPort TX IP version 2.1.0 requires the video input to provide blanking interval between active horizontal video lines to ensure correct video data packing. Failure symptoms include no video image output or black screen, even though ...
6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo. Figure 1: ...
PCIe IP Soft-DMA Mode: DMA Reset Required on Error Interrupt Detection
Description: In PCIe Soft-DMA mode, when an error condition occurs, the DMA IP asserts an interrupt to notify the Host of the detected error. If this interrupt is not properly handled and the DMA is not reset, the system may enter an unrecoverable ...

6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

Related Articles

PCIe DMA in Ring Buffer Operation mode unable to be stopped

7192 - PCIe for Nexus FPGAs: Why do PCIe Configuration Space registers (i.e. Device ID, Vendor ID, etc) not persist after first enumeration?

DisplayPort TX IP Version 2.1.0 does not support back-to-back video input without blanking interval

6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

PCIe IP Soft-DMA Mode: DMA Reset Required on Error Interrupt Detection