3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?
The Peripheral Component Interconnect Express (PCIe) endpoint IP we have currently can support only up to 8 Message Interconnect Express (MSI) interrupts.
This number of MSI interrupts available for the user can be checked in 'Multiple Message Capability' register of 'Message Control Register' of the PCIe Configuration space.
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4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?
Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...
3674 - LatticeECP2/ECP3: In Peripheral Component Interconnect Express (PCIe), when an endpoint is in the process of transmitting data to the Root Complex, is the endpoint allowed to send a parallel interrupt?
Description: Yes, when a transaction is in progress from an endpoint of PCIe IP core to the Root Complex, the endpoint can raise a parallel interrupt. However, the interrupt raised by the endpoint is kept in queue and will be processed after ...
7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?
Solution: To successfully use the MSI Interrupt, the user needs to perform the workaround below. Uncheck the box for "Disable Legacy Interrupt" to enable the Legacy Interrupt. This is a controller code requirement. 'MSI pending bit' = 1 alone does ...
3197 - LatticeECP3: Why some interrupts do not reach from PCIe core to CPU, while giving 1 ms interrupt signal to “inta_n” of PCIe core, and then monitoring interrupts at CPU side?
Out of 1000 interrupts, approximately 300 reaches to CPU, when PCIe core’s interrupt assert and de-assert gap is 8 clock duration of wb_clk. When the IP detects that inta_n is asserted low, it needs 8 clocks to create the ASSERT_INTA packet. In case ...
3606 - LatticeECP3: Can we change the DEVSEL parameter to SLOW for the PCIe IP (Peripheral Component Interconnect Express) configuration space?
No, the PCIe (Peripheral Component Interconnect Express) base specification clearly says that the DEVSEL TIMING parameter does not apply to PCIe Express Configuration space and is hardwired 0 by default. This means the DEVSEL TIMING parameter is ...