4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?
Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other.
The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 MSI interrupts at a time. The 'msi' port available on the PCIe IP is an 8-bit bus [7:0], where bit 0 of the bus refers to MSI [0] and bit 7 refers to MSI [7].
Solution: To implement multiple MSI requests, consider the following example and the image below:
If there is a requirement of 4 multiple MSI signals and the MSI bus was set to a value of '7', then MSI [2], MSI [1], and MSI [0] are requested. For example, if the Message Data Register is set to a value of "16'h9999", the PCIe IP core generates a MSI TLP (Transaction Layer Packet) with the data field as "16'h9989" for MSI [0], "16'h9999" for MSI [1] and "16'h99A9" for MSI [2].
Note: All the MSI TLPs are sent back to back, one after the other, to the RC (Root Complex).
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