4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other.

The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 MSI interrupts at a time. The 'msi' port available on the PCIe IP is an 8-bit bus [7:0], where bit 0 of the bus refers to MSI [0] and bit 7 refers to MSI [7].

Solution: To implement multiple MSI requests, consider the following example and the image below:

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4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

Related Articles

3515 - PCIe of LatticeECP3: How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe (Peripheral Component Interconnect Express) Endpoint IP core?

3606 - LatticeECP3: Can we change the DEVSEL parameter to SLOW for the PCIe IP (Peripheral Component Interconnect Express) configuration space?

3674 - LatticeECP2/ECP3: In Peripheral Component Interconnect Express (PCIe), when an endpoint is in the process of transmitting data to the Root Complex, is the endpoint allowed to send a parallel interrupt?

2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?