2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

Version 5.2 of the Lattice PCI Express IP includes an update to use the reset sequence (instead of the 4ms reset timer) requiring the reference clock from the SERDES to be enabled to the fabric. You likely use a .txt file from an earlier version which does not enable the reference clock so the PCS/PCIe core is stuck in reset. Refer to the steps the steps below to correct the issue.

For bitstream generation

Copy the latest version of .txt (from the generated core directory) to your Lattice Diamond project directory
Rerun bitgen to regenerate the bitstream. There is no need to resynthesize/re- place and route the design.

For simulation

Copy the latest version of .txt (from the generated core directory) to your Lattice Diamond project directory
Rerun simulation

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2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

2691 - PCI Express IP: Why does the TXPLL no longer lock in my PCIe design when I migrate to the latest version of the Lattice PCI Express IP?

Related Articles

4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

7763 - I3C Controller IP - Where can I download the Out of the Box Design Example

2069 - LatticeECP3: What is the usage of WB_CTI_I signal in the Lattice PCI Express Scatter Gather DMA Demo design?

1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

7158 - CertusPro-NX/PCI Express: Why does PCIe Gen3x1 and Gen3x4 simulation takes longer time to link-up?