7193 - PCIe for Nexus FPGAs: How to generate MSI Interrupts with PCIe x1 IP core?
Solution:
To successfully use the MSI Interrupt, the user needs to perform the workaround below.
Uncheck the box for "Disable Legacy Interrupt" to enable the Legacy Interrupt. This is a controller code requirement.
'MSI pending bit' = 1 alone does not automatically trigger an MSI message. It is just an indicator to the core that an MSI interrupt needs to be delivered. The core needs to write to the MSI Message Address Register (MMAR) and MSI message data register (MDR) to send message to the device.
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