6863 - PCIe for Nexus FPGAs: Is there other way to access the PCIe PLL status and pipe_rstn aside from LMMI?

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• 6247 - PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

  Solution: DMA support must be enabled to access the PCIe endpoint through AHB-lite. The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master. For more information, refer ...

• 6961 - PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?

  Description: There are some parameters that cannot be configured using LMMI. Example, in these 2 parameters: a) Target Link Speed – this is possible. The LMMI write needs to happen before PHY out of reset b) Use TLP Interface – this is not possible ...

• PCIe DMA in Ring Buffer Operation mode unable to be stopped

  Title: PCIe DMA in Ring Buffer Operation Mode Cannot Be Stopped Unexpectedly Issue Description: When the PCIe DMA is configured to operate in Ring Buffer DMA mode for continuous transfers, the DMA operation cannot be stopped unexpectedly. If a device ...

• 7002 - PCIe for Nexus FPGAs: Where to download the PCIe Demo driver source code for Linux and Windows?

  Description: The PCIe demo driver source code for Linux and Windows can be downloaded from below link: Scroll down the page and choose the appropriate PCIe Demo designs from the list. ...

• 6900 - PCIe for Nexus FPGAs: How can the PCIe configuration space settings in the RTL of the demo be interpreted?

  Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo. Figure 1: ...