7316 - All Nexus / PCIe: PCIe assignment of 2GB BAR size for 64-bit BAR addressing.

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• 1301 - PCIe: What Transaction Layer Packets (TLPs) header format is used for 64-bit addressing?

  PCIe supports both 32-bit and 64 bit addressing. For 32-bit addressing a 3-DW header is used, containing just 32-bits of address info. For 64-bit addressing, a 4-DW header is used, with the extra DW holding the additional 32-bits of addressing.

• 323 - What are the definitions of the BAR bits in PCI/PCIe application?

  The bit definitions of BAR for memory base address register are: Bit 0: reserved to 0 as memory space indicator. Bit 2~1: 00 indicates 32-bit access space; while 11 indicates 64-bit access space. Bit 3: 1 indicates that the memory is prefetchable, ...

• 6104 - PCIe: Does Lattice FPGA's PCIe SGDMA memory addressing allows beyond 4GB?

  Description: Technically there is no restriction on Lattice's FPGAs which makes us not allow memory addressing beyond 4GB. That is more on the driver side. There are some FPGA solutions which already has beyond 4GB, CrossLink-NX, Certus-NX, and ...

• 7474 - All Nexus/PCIe: Does MSI pending bits are writable?

  The MSI pending bits are writable through UCFG and it is read-only through PCIe link access.

• 7206 - PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core and PCIe X4 IP Core?

  The Transmit Buffer and Receive Buffer size is 2 kByte each. These RAM buffer sizes are fixed because it is a Core internal RAM, so the negotiated Maximum Payload Size (MPS) size will determine how many TLPs can be stored. For instance, in the ...