1301 - PCIe: What Transaction Layer Packets (TLPs) header format is used for 64-bit addressing?

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• 7316 - All Nexus / PCIe: PCIe assignment of 2GB BAR size for 64-bit BAR addressing.

  Description: There is a known bug in the PCIe IP GUI wherein the 64-bit BAR addressing requires that the BAR size be >/= 4 GB only. Solution: As a workaround, the user can write the Resizable BAR Capability Configuration (0,1,2,3,4,5) using LMMI or ...

• 6934 - PCIe for Nexus FPGA: How to write the Link Layer Configuration Space Registers on PCIe device?

  Solution: 1. Defining the usr_lmmi_offset_i [16:2] a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 à word aligned offset of base + offset address 2. Write “1’b0” on ...

• 7560 - LatticeECP3\ECP5: What is the PCIe Advanced Error Reporting header format of err_tlp_header[127:0]?

  Description: The 128-bit AER bus of err_tlp_header[127:0] Header Word 0 starts at [127:96]. The interpretation is as below: [127:96] - Header Word 0 (Fmt, Type, TC, TD, EP, Attr, Length) [95:64] - Header Word 1 (Requester ID, Tag, Last DW BE, First ...

• 1104 - LatticeECP3/ECP5: What are Link CRC (LCRC) and End to End Cyclic Redundancy Check (ECRC), and how are they used?

  Description:Peripheral Component Interconnect Express (PCIe) provides two different CRC tests for the transfer of data. The LCRC, or Link CRC, is handled in the data link layer. The optional ECRC, or endpoint CRC, is handled in the transaction layer. ...

• 6447 - CertusPro-NX PCIe: Does both Quad 0 and Quad 1 support hard IP block of PCIe link layer?

  CertusPro-NX only supports the hard IP block PCIe link layer on Quad 0. For more information, refer to second paragraph of section '11.1. PCI Express Mode' on FPGA-TN-02245.